System-on-a-chip (SOC) technology is the best known of several methodologies that attempt to achieve new levels of component integration. But the SOC approach has severe drawbacks that make it unsuitable for all but the highest-volume applications. These limitations include: the lack of component upgrade flexibility; addition of unnecessary levels of complexity that increase component cost, design time, and test time; and increased restrictions on printed-circuit board layout, performance, and power dissipation.

Consequently, designers are turning to alternative types of system-level integration that use module-based techniques in computer and communications applications, to reduce size, weight, and power. A new generation of system-level packaging, termed system-in-a-package (SIP), is emerging which combines multiple ICs and discrete components into a single package. This approach ensures component upgrade flexibility and takes advantage of the design simplicity of separate ICs to minimize cost, design time, and test time. SIP adds the further benefits of lower power and higher bandwidth by providing an opportunity to implement new bus standards that leverage high speed, low noise SIP interconnect (see Figure 1).

Flexibility, complexity, and costs

System designers want the flexibility of upgrading each IC in their designs for function, speed, power, and/or cost, without being forced to upgrade all of the system's IC content at once. For instance, the processor may go through a major revision every two years, the memory will undergo a shrink every six months, and the ASIC or ASSP will change every time a bus standard evolves. But the SOC approach to integration doesn't allow this flexibility.

Figure 1 - Differenial rates of system IC upgrades

A flexible integration strategy is required to accomodate different IC upgrade schedules.

The SOC and SIP approaches also differ in several other critical ways. Integrating intellectual property (IP) in a SIP is an entirely different process from integrating IP in an SOC. The SOC approach introduces a significant level of complexity and cost into chip design and manufacturing. A standard wafer process is optimized for either logic or memory, but mixing the technologies will require additional mask steps beyond what would be required to create a logic-only or memory-only device. Wafer processing is only part of the complexity problem. Different technologies, like digital and analog for instance, have different design rules, and in many cases different geometries. To integrate these disparate technologies the fab must create new process steps, which further increase mask count and NRE. Even more important, however, is the increased cost of wafer processing and the increase in defect density from additional process steps. The combination of more masks, more defects, and larger die causes cost per die to escalate.

The SIP approach reduces total cost at the system level. ICs designed and manufactured as separate die produce the lowest cost components. Assembly cost, while proportional to the number of IC and discrete components in the system, is similar to single chip assembly. The smaller footprint of a SIP vs. separately packaged devices reduces PC board area. And the reduced number of external I/O reduces layer count and drilled via count, further reducing costs. In addition, many passive components, such as resistive terminators and local bypass capacitors, may be eliminated entirely from the bill of materials. In summary, the SIP approach retains the design and manufacturing advantages of separately packaged parts, while achieving the final assembly advantages of SOC.

Design and test time

The design time for mixed technology integration in SOCs is also longer than is required for the design of separate ICs. It is harder to ensure that "buried" interfaces work correctly and don't interfere electrically with one another. For example, digital-switching noise injected into the substrate will be coupled into sensitive analog circuits. The EDA tools available to predict and control these complex interactions are limited in scope, and require substantial monetary and time investments.

Mixed-technology designs are difficult and expensive to test. Testing buried components compounds the design time, as well as increases tester time. Since tester types also vary with technology, test equipment is multiplexed, resulting in poorer utilization, and hence greater cost. In the fast time-to-market environment designers work in today, all of these factors directly impact the viability of a project and its success.

Interfaces for a SIP between die are also buried, from the point of view of the outside of the package. But the distinction and the advantage are that the separate die that comprise the SIP can be tested by standard test flows. The only additional tests required for buried busses are JTAG Extest, a typical requirement for state-of-the-art PC board designs.

Interconnect issues

Another significant difference between SOC and SIP methodologies is the benefits that SIP technology brings to system-level interconnect. These include lower power and noise, which, in turn, allow higher operating frequency and higher bandwidth. For example, in Alpine's (Campbell, CA) SIP approach, the substrate is attached to the PC board using an area array packaging technique that provides a very low inductance path from the PC board to the ICs, while also improving heat dissipation. The company's SIP methodology is based on a patented Microboard substrate, developed with IC processing techniques that allow very fine line width and via geometry. The Microboard substrate utilizes a copper on low-k dielectric interconnect that offers very high routing resources with high-speed/low noise 50-Ohm signal paths. Solder bump technology provides ultra-low (less than 50 pH) inductance connections. Eliminating the physical packages allows ICs to be placed very close together, which further reduces chip-to-chip bus capacitance, as well as parasitic inductance in the power distribution network. This, in turn, reduces power wasted in charging the bus. Alternately, lower bus power and lower switching noise allow a higher bus frequency at a fixed power level.

Figure 2 - Cross-section of SIP system interconnect

SIP technology allows lower power and noise in system-level interconnect.

In most electronic applications, once the software reference platform and the hardware architectural design have been defined, the only remaining option to reduce active power is to minimize capacitance in the PC board and the IC package (Pbus capacitance = 1/2 Fdata*Cbus*Vdd2, where Fdata is typically 1/2 the bus frequency). Bus capacitance is the sum of the capacitance of the I/O driver circuit and the associated package pin, all trace and via capacitance in the PC board, and the pin and I/O receiver circuit capacitance in the load.

A design that takes up less PC board area and includes fewer components optimized for the particular substrate technology can minimize overall costs. SIP benefits are thus greatest when the interface between components is optimized for the interconnect medium. In contrast to SOC, a SIP contains multiple components combined into a single package that is typically similar in size to the package of one of the components. One definition of the SIP approach that clearly differentiates it from other multi-chip packages is the integration of components that are optimized specifically for a system-level package. For example, when ICs are optimized for the high-speed and high I/O density characteristics of the Microboard substrate, system bandwidth can increase dramatically, while reducing power consumption. Optimization at the die not only provides significant benefits to the system, but can also reduce the cost of the die. When a system is partitioned into separate components, versus a single SOC, the components can be optimized for manufacturing cost as well as performance. The wafer fabrication process can be simplified, yields can be improved, and die size reduced.

In addition to reducing die area by partitioning functions like memory, logic, and analog into separate die, changes to the interface circuitry can produce a more efficient die layout. I/O drivers sized for low capacitance interconnect are significantly smaller in area and consume much less power than a typical high-current, off-chip driver. Additional savings in size and power are achieved by resizing the I/O pre-driver circuitry. The use of ball grid array pads allows small I/O drivers to be placed closer to their functional source or load, further reducing on-chip "river" routing. Array pads allow a much larger number of I/O ports which can eliminate on-chip multiplexing. Array pads for connections inside of the SIP are essentially "free," since the incremental cost per pad is insignificant (see Figure 2).

Voltage reduction or simplification is also desirable. Bus routing that "stays" inside the SIP can operate at a lower voltage. In some cases, a high voltage supply formerly required for off-chip interfaces can be eliminated entirely from the IC. This not only reduces power but also simplifies IC design and manufacturing. Full optimization occurs when the system interconnect and die are co-designed. Perhaps the most significant example occurs when the low-loss copper routing available in the SIP substrate is used to augment or replace on-chip routing to maintain Vdd levels near the center of the die, or to reduce clock delay and skew. In some cases, this can eliminate the need to add expensive copper processing to the IC wafer. Because SIP technology allows additional I/Os, and consequently additional busses, it will lead to new definitions for bus standards that are matched to the ICs.

Innovative bus standards

The bus standards that have been developed for PC boards are too restrictive, consume too much power, and retard bandwidth. To save I/O pins, many existing busses multiplex data and command onto fewer wires than would exist logically. The act of multiplexing always adds latency and is likely to increase power dissipation by causing extraneous bit transitions on wires. (This is easily seen because the natural tendency of a particular bit weight, especially in the higher order bits, is to remain at the same value.) Multiplexed architectures force dissimilar bits to coexist on a physical wire, leading to a source of extra power consumption. The technique of doubling the number of pins to separate input and output paths to avoid bus turnaround and contention inefficiency are very rarely used off die, although this is a routine technique to improve performance on die.

In addition, SOC bus standards such as VSIA (Virtual Socket Interface Alliance) or proprietary busses such as those offered by IBM (Armonk, NY) and LSI Logic (Milpitas, CA), add unnecessary logic to accommodate testing, and impede performance by compromising IP blocks to fit a particular vendor's "platform." For instance, VSIA would require existing IP blocks to be modified in order to work with the bus standard, or require logic "wrappers" to interface to it, adding complexity and latency.

Yet, at the high-performance end of electronic systems, dramatic increases in bandwidth are continually being required, rising from the range of 0.5 Gbyte/sec to 1 byte/sec today to 10 and even 100 Gbytes/sec in the foreseeable future. Faster bus-switching rates will not provide sufficient increases in bandwidth. Instead, wider data busses are needed, but wider and faster busses between packaged components are increasingly difficult and expensive to design, manufacture, and test with traditional PC board technology. Proof of this difficulty is evident in data bus widths of only 18 bits for high-speed interconnect such as the Rambus channel architecture. Even at 800 MHz, this bus only supplies a modest 1.6 Gbytes/sec, which barely meets existing needs today while also consuming several watts of excess power. The Rambus channel architecture was the result of years of extremely focused engineering effort, illustrating the especially significant cost going forward of developing ultra-high bandwidth, off-package busses, as well as the intensive engineering that will be required to design systems with them.

Figure 3 - Moving to optimized ICs and busses

A computer system with optimized ICs and busses allows significant improvement in bandwidth while reducing power in SIP implementations.

Lower power may be achieved by differential signaling compared to single-ended busses such as Rambus, but at the price of doubling the number of I/O pins per bit transmitted, a difficult tradeoff when using separately packaged parts. The internal performance of ICs will continue to increase, and their internal data bandwidth will accelerate, but wherever chip-to-chip communication is required the system interconnect becomes a significant bandwidth bottleneck. In many ways, off-package busses violate Rent's rule for the desired number of interconnects between logic blocks to maintain bandwidth.

SOC can correct this, but at the costs described above. SIP also enables interconnect size closer to the theoretically desired number. These considerations are becoming especially critical in the fast-growing areas of high-bandwidth, high-volume computer and communications systems - such as multiprocessor-based systems, shared memory systems, and network switches and routers - as well as in portable consumer systems. System busses - such as PCI and PC100 in the computer space, or Utopia in the network space - have been limited to 16 to 64 bits. Emerging 128-bit and higher versions of these busses have been limited to point-to-point applications such as 3D graphics.

The SIP approach provides several opportunities to define bus standards that take into account the benefits of high-density interconnect without compromising functionality or performance. Techniques afforded by this technology to improve bandwidth include increased data frequency, increased data width, reduced bus latency, reduced settling time requirements, and eliminating bus turnaround. Extending on-chip techniques to all of the components in a SIP can produce chip-to-chip bandwidths that meet or exceed single-chip SOC capabilities.

The SIP approach can be phased in to achieve the most optimal solution for existing products, which allows system designers to trade off product improvements with time to market. For instance, even though existing off-package busses are inefficient for previously mentioned reasons, an acceptable transitional solution can use several instances of a bus to achieve higher bandwidth when the routing density of SIP comes into play.

Cloning busses

By "cloning" existing busses, and defaulting them to unidirectional operation, IP blocks can be preserved intact. Many I/Os are now available with programmable drive strength and voltage. This means that existing IP can achieve significant power and speed benefits by driving a lower swing signal, as long as off-module interfacing isn't required. Ideally, once a system designer has adopted a SIP approach, co-design that comprehends both on-die and off-die bus design becomes the preferred method to maximize benefits.

By treating off-die busses and on-die SOC busses similarly, many of the barriers to architectural innovation are removed. That is, by defining a bus that suitably intersects the routing density of both the SIP and the on-die density, re-partitioning of the system can be an additional route to the lowest cost. For instance, integration of a level of cache hierarchy can be delayed by one process generation or more, reserving "expensive" transistors in the microprocessor process for logic, while moving SRAM to "cheap" transistors of multi-sourced SRAM vendors. Busses or groups of busses in the range of 512 bits wide fit easily in the area of interconnect density overlap for on- and off-die busses.

Because the time of flight is comparable for SIP and on-die system interconnect in copper processes, the architectural distinction between on-die and off-die interconnect is further reduced. Alpine's technology supplies 50 pS/cm delays, comparing very favorably to RC delays of on-die wires. State-of-the-art signaling choices for future designs - such as clock delay time borrowing, "globally asynchronous/locally synchronous," and self-timed techniques, commonly used on leading-edge die - can be successfully deployed in SIP.

However, these techniques entail a lot of design challenges and risk when they are used in an off-die package.

In conclusion, SIP occupies a "sweet spot" between SOC and traditional, separately packaged parts. SIP provides the desired SOC performance benefits of lower power, higher speed, and smaller footprint, while avoiding the high cost of increased fab, test, and time-to-market delays.

Sam Beal is vice president of marketing for Alpine Microsystems, Inc. Dr. Beal joined the company from Actel, where he established applications engineering and product planning teams. Prior to Actel, he was a Senior Member of the Technical Staff at Texas Instruments.

David Sherman is vice president of engineering for Alpine Microsystems, Inc. Previously, he was senior staff engineer at Cirrus Logic. Before Cirrus, he was the founder and director of hardware engineering for Shographics, after working as an engineer at Atari Games. To voice an opinion on this or any other article in Integrated System Design, please e-mail your comments to sdean@cmp.com.